Computer Architecture Mind Map
Algorithm & Systems VisualizationsEvery computer architecture visualization on this site on one map. The branches are the main ideas. Each leaf is a page; the grey line under it is the one thing to remember about it. Click a branch to focus on it, click a page to open it.
1. How the map is organized
Ask what a page is about and where it sits in the stack:
- Is it about wires and gates? No memory of the past: combinational logic. Holds state on a clock: sequential logic.
- Is it about instructions? Writing, translating or calling code: MIPS software. The hardware that runs one instruction: the processor.
- Is it about speed? Running many instructions at once: pipelines and parallelism. Getting data to the core: memory and I/O.
2. The branches side by side
| Branch | Main unit | Key question | Key number |
|---|---|---|---|
| Abstraction and numbers | bit | what does this pattern mean? | range and precision |
| Combinational logic | gate | what is the output? | delay t_pd |
| Sequential logic | flip-flop | what is the next state? | setup and hold slack |
| MIPS software | instruction | how does C become machine code? | instruction count |
| The processor | datapath | how does one instruction run? | CPI × cycle time |
| Pipelines and parallelism | stage, core | how many run at once? | hazards, speedup |
| Memory and I/O | cache line, page | where is the data? | hit rate, AMAT |
3. Five facts to remember
- Execution time = instructions × CPI × clock period; every design trades these three.
- The clock period must cover the slowest register-to-register path plus setup time.
- Pipelining raises throughput, not the latency of one instruction; hazards cost stalls.
- Caches work because programs reuse recent data (temporal) and nearby data (spatial locality).
- Amdahl's law: the serial part of a program limits the speedup from more cores.
See all computer architecture pages in the index, or the other mind maps.